DARPA: 3D IC Design

CoolCAD Electronics, LLC.

387 Technology Drive, College Park, MD, USA

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DARPA SBIR: CAD Tool Development for 3D Integrated Circuits

3D integrated circuits have the potential of increasing the functionality of electronics. By transforming from the existing 2D paradigm to 3D, significantly more functionality can be fit into a finite volume. Processor structures can be envisioned where input/output is directly connected to memory or bus lines in the vertical or third dimension, thereby enabling parallel processing structures for digital IC’s. This has the potential of greatly increasing data bandwidth in digital processors. 3D integration can significantly reduce the need for multi-chip modules by integrating functionalities typically found in different chips into a single 3D structure thereby eliminating the intrinsic delay resulting from passive I/O structures.3D integration can be very advantageous for passive elements as well, providing the infrastructure to fabricate passive structures that could be significantly improved over their 2D counterparts. For example, existing on-chip inductors typically have very low quality factor (Q) due to their largely planar geometry. By taking advantage of 3D integration, the geometry of inductors could be extended to 3D thereby increasing both inductance and Q. Furthermore, on-chip antenna design could become increasingly viable by taking advantage of 3D geometries.

Project Phase 1 Plan:

We plan to develop CAD design tools which both facilitate the design of 3D circuits and circuit elements, as well as tools to predict the parasitic effects resulting from 3D integration. We will be developing an iterative process to achieve optimized 3D design based on intrinsic 3D architectural advantages and following constraint:

3D interconnect delay
Coupled transistor operation and 3D heat generation
3D functionality-based floorplanning
3D design using 2D modules and 2D-to-3D interface.

Specifically during phase 1, we will be developing a comprehensive CAD tool with the following components.

Prediction of heat generated and the resulting temperature as a function of location in 3D IC’s
Prediction of device and circuit performance as a function of local IC temperature.
Prediction of the unintentional coupling of electromagnetic signals between different locations in a 3D IC.
Prediction of the parasitic resistivity, capacitance and inductance of 3D interconnect structures.
Calculation of the performance of passive circuit elements that are implemented in 3D IC’s. For example, inductor and antenna structures with improved performance using 3D integration.
Development of optimization sub-circuit routing and placement algorithms that take local temperature and RC, RL and RLC effects into account for laying out integrated circuits in 3D.
Tools which help to enable standard simulation languages and layout tools, such as Verilog and Cadence, for use with 3D integration.

The final part of this Phase 1 effort will be to utilize our CAD methodologies and tools to design a new 3D IC and submit it for fabrication.

3D-IC’s will only be realizable if accurate 3D CAD tools are made available. This work is key to achieving this.

3D Thermal Map

3D Place & route

3D Layout and Routing

3D Delay

3D Delay Calculation

Layout

Flowchart for Complete 3D IC CAD

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